On the robustness of R-2R ladder DACs

A model of the linear R-2R ladder digital-to-analog converter (DAC) is developed in terms of the ratios of the effective resistances at the nodes of the ladder. This formulation demonstrates clearly why an infinite number of different sets of resistors can produce the same linearity error and shows how this error can be reduced by trimming. The relationship between the weights of the bits and the resistor ratios suggests appropriate trimming, design, and test strategie

Mathematical analysis of prime modulus quantizer MASH digital delta-sigma modulator

A MASH digital delta-sigma modulator (DDSM) is analyzed mathematically. It incorporates first-order error feedback modulators (EFM) which include prime modulus quantizers to guarantee a minimum sequence length M. The purpose of this analysis is to calculate the exact sequence length of the aforementioned MASH DDSM. We show that the sequence length for an lth-order member of this modulator family is M for all constant inputs, and for all initial conditions, where M is the sequence length of the constituent first-order prime modulus quantizer EFMs.

Hardware reduction in digital delta-sigma modulators via error masking - part II: SQ-DDSM

In this two-part paper, a design methodology for reduced-complexity digital delta-sigma modulators (DDSMs) based on error masking is presented. Rules for selecting the wordlengths of the stages in multistage architectures are elaborated. We show that the hardware requirement can be reduced by up to 20% compared with a conventional design, without sacrificing performance. Simulation results confirm theoretical predictions. Part I addresses multistage noise-shaping DDSMs, whereas Part II focuses on single-quantizer DDSMs

Architectures for maximum-sequence-length digital delta-sigma modulators

In this paper, we extend the idea developed in some of our earlier works of using output feedback to make the quantization step in a digital delta-sigma modulator (DDSM) appear prime. This maximizes the cycle lengths for constant inputs, spreading the quantization error over the maximum number of frequency terms, and consequently, minimizing the power per tone. We show how this concept can be applied to multibit higher order error-feedback modulators (EFMs). In addition, we show that the idea can be implemented in a class of single-quantizer DDSMs (SQ-DDSM) where STF (z) = z(-L) and NTF (z) = (1 - Z(-1))(L)

The role of synchronization in digital communications using chaos - part III: performance bounds for correlation receivers

For pt. II, see ibid., vol. 45, p. 1129-40 (1998). In a digital communications system, data is transmitted from one location to another by mapping bit sequences to symbols, and symbols to sample functions of analog waveforms. The analog waveform passes through a bandlimited (possibly time-varying) analog channel, where the signal is distorted and noise is added. In a typical conventional system, the analog sample functions sent through the channel are weighted sums of one or more sinusoids, called basis functions; in a chaotic communications system, the sample functions are segments of chaotic waveforms. This three-part paper shows in a tutorial manner how the theory of conventional telecommunications systems can be applied to chaotic modulation schemes. In addition, it discusses the latest results in the field of chaotic communications. In Part III, examples are given of chaotic communications schemes with and without synchronization, and the performance of correlator-based systems is evaluated in the context of noisy, bandlimited channel

Reduced complexity MASH delta-sigma modulator

A reduced complexity digital multi-stage noise shaping (MASH) delta-sigma modulator for fractional-N frequency synthesizer applications is proposed. A long word is used for the first modulator in a MASH structure; the sequence length is maximized by setting the least significant bit of the input to 1; shorter words are used in subsequent stages. Experimental results confirm simulation

Statistical properties of first-order bang-bang Pll with nonzero loop delay

A method to solve the stationary state probability is presented for the first-order bang-bang phase-locked loop (BBPLL) with nonzero loop delay. This is based on a delayed Markov chain model and a state How diagram for tracing the state history due to the loop delay. As a result, an eigenequation is obtained, and its closed form solutions are derived for some cases. After obtaining the state probability, statistical characteristics such as mean gain of the binary phase detector and timing error variance are calculated and demonstrated

Hardware reduction in digital delta-sigma modulators via error masking - part I: MASH DDSM

Two classes of techniques have been developed to whiten the quantization noise in digital delta-sigma modulators (DDSMs): deterministic and stochastic. In this two-part paper, a design methodology for reduced-complexity DDSMs is presented. The design methodology is based on error masking. Rules for selecting the word lengths of the stages in multistage architectures are presented. We show that the hardware requirement can be reduced by up to 20% compared with a conventional design, without sacrificing performance. Simulation and experimental results confirm theoretical predictions. Part I addresses MultistAge noise SHaping (MASH) DDSMs; Part II focuses on single-quantizer DDSMs.

Prediction of the Spectrum of a Digital Delta–Sigma Modulator Followed by a Polynomial Nonlinearity

This paper presents a mathematical analysis of the power spectral density of the output of a nonlinear block driven by a digital delta-sigma modulator. The nonlinearity is a memoryless third-order polynomial with real coefficients. The analysis yields expressions that predict the noise floor caused by the nonlinearity when the input is constant

Linear model-based testing of ADC nonlinearities

In this brief, we demonstrate the procedures of linear model-based testing for the example of a 12-b Nyquist-rate analog-to-digital converter (ADC). In a production test environment, we apply this technique to two wafer lots of devices, and we establish that the model is robust with respect to its ability to reduce the uncertainty of the test outcome. Reducing this uncertainty is particularly beneficial for higher resolution devices, for which measurement noise increasingly corrupts the measured "signal" that is the nonlinearity of the device under test